%0 Conference Paper %1 conf/vlsi/GiacominG18 %A Giacomin, Edouard %A Gaillardon, Pierre-Emmanuel %B VLSI-SoC %D 2018 %I IEEE %K dblp %P 107-112 %T Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2018.html#GiacominG18 %@ 978-1-5386-4756-1

@inproceedings{conf/vlsi/GiacominG18, added-at = {2019-02-26T00:00:00.000+0100}, author = {Giacomin, Edouard and Gaillardon, Pierre-Emmanuel}, biburl = {https://www.bibsonomy.org/bibtex/2d52dfedb4765da950879dc0bdbcf2a16/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2018soc}, ee = {https://doi.org/10.1109/VLSI-SoC.2018.8644747}, interhash = {9b571e9bb557cf971adf8104e8495e5c}, intrahash = {d52dfedb4765da950879dc0bdbcf2a16}, isbn = {978-1-5386-4756-1}, keywords = {dblp}, pages = {107-112}, publisher = {IEEE}, timestamp = {2019-10-17T14:02:23.000+0200}, title = {Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2018.html#GiacominG18}, year = 2018 }