%0 Conference Paper %1 conf/cisis/VillamonLMBBG09 %A Villamón, Francisco Gilabert %A Ludovici, Daniele %A Medardoni, Simone %A Bertozzi, Davide %A Benini, Luca %A Gaydadjiev, Georgi Nedeltchev %B CISIS %D 2009 %E Barolli, Leonard %E Xhafa, Fatos %E Hsu, Hui-Huang %I IEEE Computer Society %K dblp %P 681-687 %T Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints. %U http://dblp.uni-trier.de/db/conf/cisis/cisis2009.html#VillamonLMBBG09 %@ 978-0-7695-3575-3

@inproceedings{conf/cisis/VillamonLMBBG09, added-at = {2023-03-24T00:00:00.000+0100}, author = {Villamón, Francisco Gilabert and Ludovici, Daniele and Medardoni, Simone and Bertozzi, Davide and Benini, Luca and Gaydadjiev, Georgi Nedeltchev}, biburl = {https://www.bibsonomy.org/bibtex/2b9f5edeeb7331d10f2d3f8cfe910d6b2/dblp}, booktitle = {CISIS}, crossref = {conf/cisis/2009}, editor = {Barolli, Leonard and Xhafa, Fatos and Hsu, Hui-Huang}, ee = {https://doi.ieeecomputersociety.org/10.1109/CISIS.2009.30}, interhash = {9cddd493d203acbf26c31847ace1b09c}, intrahash = {b9f5edeeb7331d10f2d3f8cfe910d6b2}, isbn = {978-0-7695-3575-3}, keywords = {dblp}, pages = {681-687}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:52:45.000+0200}, title = {Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.}, url = {http://dblp.uni-trier.de/db/conf/cisis/cisis2009.html#VillamonLMBBG09}, year = 2009 }