%0 Journal Article %1 journals/iet-cdt/ShelburnePAJMF10 %A Shelburne, Matthew %A Patterson, Cameron D. %A Athanas, Peter %A Jones, Mark %A Martin, Brian S. %A Fong, Ryan %D 2010 %J IET Comput. Digit. Tech. %K dblp %N 3 %P 159-169 %T MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip. %U http://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt4.html#ShelburnePAJMF10 %V 4

@article{journals/iet-cdt/ShelburnePAJMF10, added-at = {2020-07-14T00:00:00.000+0200}, author = {Shelburne, Matthew and Patterson, Cameron D. and Athanas, Peter and Jones, Mark and Martin, Brian S. and Fong, Ryan}, biburl = {https://www.bibsonomy.org/bibtex/2ce1fe81cc71539d24fd09780d33d1a83/dblp}, ee = {https://doi.org/10.1049/iet-cdt.2009.0009}, interhash = {9f5446b6963645e51f59923ffb0f4885}, intrahash = {ce1fe81cc71539d24fd09780d33d1a83}, journal = {IET Comput. Digit. Tech.}, keywords = {dblp}, number = 3, pages = {159-169}, timestamp = {2020-07-24T00:16:45.000+0200}, title = {MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip.}, url = {http://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt4.html#ShelburnePAJMF10}, volume = 4, year = 2010 }