Inproceedings,
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.
V. Kumar, K. Dhiman, M. Datar, A. Pacharne, H. Narayanan, and S. Patkar.VLSID, page 409-414. IEEE Computer Society, (2016)
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- conf/vlsid/KumarDDPNP16
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- inproceedings
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- VLSID
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- 2016
- pages
- 409-414
- publisher
- IEEE Computer Society
- crossref
- conf/vlsid/2016
- ee
- https://doi.ieeecomputersociety.org/10.1109/VLSID.2016.84
- isbn
- 978-1-4673-8700-2
- url
- http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#KumarDDPNP16
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- please select -%0 Conference Paper
%1 conf/vlsid/KumarDDPNP16
%A Kumar, Vinay B. Y.
%A Dhiman, Kulshreshth
%A Datar, Mandar
%A Pacharne, Akash
%A Narayanan, H.
%A Patkar, Sachin B.
%B VLSID
%D 2016
%I IEEE Computer Society
%K dblp
%P 409-414
%T Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.
%U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#KumarDDPNP16
%@ 978-1-4673-8700-2
@inproceedings{conf/vlsid/KumarDDPNP16,
added-at = {2023-03-24T00:00:00.000+0100},
author = {Kumar, Vinay B. Y. and Dhiman, Kulshreshth and Datar, Mandar and Pacharne, Akash and Narayanan, H. and Patkar, Sachin B.},
biburl = {https://www.bibsonomy.org/bibtex/24be53e793b39da69604d6b2383f13a5f/dblp},
booktitle = {VLSID},
crossref = {conf/vlsid/2016},
ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2016.84},
interhash = {a1b2d735144d18d75808267eae7ad6b5},
intrahash = {4be53e793b39da69604d6b2383f13a5f},
isbn = {978-1-4673-8700-2},
keywords = {dblp},
pages = {409-414},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T01:05:31.000+0200},
title = {Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.},
url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#KumarDDPNP16},
year = 2016
}