%0 Conference Paper %1 conf/iscas/TsaiNJAHIMCONBM23 %A Tsai, Hsinyu %A Narayanan, Pritish %A Jain, Shubham %A Ambrogio, Stefano %A Hosokawa, Kohji %A Ishii, Masatoshi %A Mackin, Charles %A Chen, Ching-Tzu %A Okazaki, Atsuya %A Nomura, Akiyo %A Boybat, Irem %A Muralidhar, Ramachandran %A Frank, Martin M. %A Yasuda, Takeo %A Friz, Alexander M. %A Kohda, Yasuteru %A Chen, An %A Fasoli, Andrea %A Rasch, Malte J. %A Wozniak, Stanislaw %A Luquin, Jose %A Narayanan, Vijay %A Burr, Geoffrey W. %B ISCAS %D 2023 %I IEEE %K dblp %P 1-5 %T Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). %U http://dblp.uni-trier.de/db/conf/iscas/iscas2023.html#TsaiNJAHIMCONBM23 %@ 978-1-6654-5109-3

@inproceedings{conf/iscas/TsaiNJAHIMCONBM23, added-at = {2023-09-30T00:00:00.000+0200}, author = {Tsai, Hsinyu and Narayanan, Pritish and Jain, Shubham and Ambrogio, Stefano and Hosokawa, Kohji and Ishii, Masatoshi and Mackin, Charles and Chen, Ching-Tzu and Okazaki, Atsuya and Nomura, Akiyo and Boybat, Irem and Muralidhar, Ramachandran and Frank, Martin M. and Yasuda, Takeo and Friz, Alexander M. and Kohda, Yasuteru and Chen, An and Fasoli, Andrea and Rasch, Malte J. and Wozniak, Stanislaw and Luquin, Jose and Narayanan, Vijay and Burr, Geoffrey W.}, biburl = {https://www.bibsonomy.org/bibtex/237a6ebf30dbd2550a84974394cea141a/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2023}, ee = {https://doi.org/10.1109/ISCAS46773.2023.10181650}, interhash = {a39cfb7897920b22897483a4df8d4568}, intrahash = {37a6ebf30dbd2550a84974394cea141a}, isbn = {978-1-6654-5109-3}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2024-04-09T21:29:17.000+0200}, title = {Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2023.html#TsaiNJAHIMCONBM23}, year = 2023 }