%0 Conference Paper %1 conf/date/LaiLWCW18 %A Lai, Yung-An %A Lin, Chia-Chun %A Wu, Chia-Cheng %A Chen, Yung-Chih %A Wang, Chun-Yao %B DATE %D 2018 %E Madsen, Jan %E Coskun, Ayse K. %I IEEE %K dblp %P 773-778 %T Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. %U http://dblp.uni-trier.de/db/conf/date/date2018.html#LaiLWCW18 %@ 978-3-9819263-0-9

@inproceedings{conf/date/LaiLWCW18, added-at = {2018-04-24T00:00:00.000+0200}, author = {Lai, Yung-An and Lin, Chia-Chun and Wu, Chia-Cheng and Chen, Yung-Chih and Wang, Chun-Yao}, biburl = {https://www.bibsonomy.org/bibtex/24f02188bb0191225b2ba99aea34d83aa/dblp}, booktitle = {DATE}, crossref = {conf/date/2018}, editor = {Madsen, Jan and Coskun, Ayse K.}, ee = {https://doi.org/10.23919/DATE.2018.8342111}, interhash = {a44ca84ecd08275917fbf2cbdd45bdda}, intrahash = {4f02188bb0191225b2ba99aea34d83aa}, isbn = {978-3-9819263-0-9}, keywords = {dblp}, pages = {773-778}, publisher = {IEEE}, timestamp = {2019-10-17T15:04:19.000+0200}, title = {Efficient synthesis of approximate threshold logic circuits with an error rate guarantee.}, url = {http://dblp.uni-trier.de/db/conf/date/date2018.html#LaiLWCW18}, year = 2018 }