%0 Journal Article %1 journals/fgcs/AmmendolaBFGGCL15 %A Ammendola, Roberto %A Biagioni, Andrea %A Frezza, Ottorino %A Geurts, Werner %A Goossens, Gert %A Cicero, Francesca Lo %A Lonardo, Alessandro %A Paolucci, Pier Stanislao %A Rossetti, Davide %A Simula, Francesco %A Tosoratto, Laura %A Vicini, Piero %D 2015 %J Future Gener. Comput. Syst. %K dblp %P 109-118 %T ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces. %U http://dblp.uni-trier.de/db/journals/fgcs/fgcs53.html#AmmendolaBFGGCL15 %V 53

@article{journals/fgcs/AmmendolaBFGGCL15, added-at = {2020-02-19T00:00:00.000+0100}, author = {Ammendola, Roberto and Biagioni, Andrea and Frezza, Ottorino and Geurts, Werner and Goossens, Gert and Cicero, Francesca Lo and Lonardo, Alessandro and Paolucci, Pier Stanislao and Rossetti, Davide and Simula, Francesco and Tosoratto, Laura and Vicini, Piero}, biburl = {https://www.bibsonomy.org/bibtex/2e75504e434c50c6333446c7659333b78/dblp}, ee = {https://doi.org/10.1016/j.future.2014.12.012}, interhash = {a7734a430acb942ac46c6ac68dd7659b}, intrahash = {e75504e434c50c6333446c7659333b78}, journal = {Future Gener. Comput. Syst.}, keywords = {dblp}, pages = {109-118}, timestamp = {2020-02-20T12:09:58.000+0100}, title = {ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.}, url = {http://dblp.uni-trier.de/db/journals/fgcs/fgcs53.html#AmmendolaBFGGCL15}, volume = 53, year = 2015 }