%0 Journal Article %1 journals/tvlsi/DobkinPG05 %A Dobkin, Rostislav (Reuven) %A Peleg, Michael %A Ginosar, Ran %D 2005 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 4 %P 427-438 %T Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#DobkinPG05 %V 13

@article{journals/tvlsi/DobkinPG05, added-at = {2020-03-11T00:00:00.000+0100}, author = {Dobkin, Rostislav (Reuven) and Peleg, Michael and Ginosar, Ran}, biburl = {https://www.bibsonomy.org/bibtex/24f6fbf47c127b8114cb4e870bbbcb95e/dblp}, ee = {https://doi.org/10.1109/TVLSI.2004.842916}, interhash = {ac65ccc70ef398602d24d48912301b97}, intrahash = {4f6fbf47c127b8114cb4e870bbbcb95e}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 4, pages = {427-438}, timestamp = {2020-03-12T11:41:27.000+0100}, title = {Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi13.html#DobkinPG05}, volume = 13, year = 2005 }