%0 Conference Paper %1 conf/iscas/WuSWS01 %A Wu, Chien-Ming %A Shieh, Ming-Der %A Wu, Chien-Hsing %A Sheu, Ming-Hwa %B ISCAS (4) %D 2001 %I IEEE %K dblp %P 206-209 %T VLSI architecture of extended in-place path metric update for Viterbi decoders. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2001-4.html#WuSWS01 %@ 0-7803-6685-9

@inproceedings{conf/iscas/WuSWS01, added-at = {2016-05-20T00:00:00.000+0200}, author = {Wu, Chien-Ming and Shieh, Ming-Der and Wu, Chien-Hsing and Sheu, Ming-Hwa}, biburl = {https://www.bibsonomy.org/bibtex/2ba4083664c6794217a6885b40713053e/dblp}, booktitle = {ISCAS (4)}, crossref = {conf/iscas/2001}, ee = {http://dx.doi.org/10.1109/ISCAS.2001.922208}, interhash = {ae657e950a275254d27bcde49bf824a0}, intrahash = {ba4083664c6794217a6885b40713053e}, isbn = {0-7803-6685-9}, keywords = {dblp}, pages = {206-209}, publisher = {IEEE}, timestamp = {2016-05-21T11:49:07.000+0200}, title = {VLSI architecture of extended in-place path metric update for Viterbi decoders.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2001-4.html#WuSWS01}, year = 2001 }