%0 Journal Article %1 journals/integration/MoiseevWK15 %A Moiseev, Konstantin %A Wimer, Shmuel %A Kolodny, Avinoam %D 2015 %J Integr. %K dblp %P 116-128 %T Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. %U http://dblp.uni-trier.de/db/journals/integration/integration48.html#MoiseevWK15 %V 48

@article{journals/integration/MoiseevWK15, added-at = {2020-02-20T00:00:00.000+0100}, author = {Moiseev, Konstantin and Wimer, Shmuel and Kolodny, Avinoam}, biburl = {https://www.bibsonomy.org/bibtex/2f578cea80d3e6630b04c8e4144174dbe/dblp}, ee = {https://doi.org/10.1016/j.vlsi.2014.03.002}, interhash = {b5da56a530fb35eb060e53f374aad253}, intrahash = {f578cea80d3e6630b04c8e4144174dbe}, journal = {Integr.}, keywords = {dblp}, pages = {116-128}, timestamp = {2020-02-21T11:54:21.000+0100}, title = {Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration48.html#MoiseevWK15}, volume = 48, year = 2015 }