%0 Conference Paper %1 conf/ica3pp/ZhuWWQLC10 %A Zhu, Danfeng %A Wang, Rui %A Wang, Hui %A Qian, Depei %A Luan, Zhongzhi %A Chu, Tianshu %B ICA3PP (1) %D 2010 %E Hsu, Ching-Hsien %E Yang, Laurence Tianruo %E Park, Jong Hyuk %E Yeo, Sang-Soo %I Springer %K dblp %P 174-185 %T A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor. %U http://dblp.uni-trier.de/db/conf/ica3pp/ica3pp2010-1.html#ZhuWWQLC10 %V 6081 %@ 978-3-642-13118-9

@inproceedings{conf/ica3pp/ZhuWWQLC10, added-at = {2017-05-26T00:00:00.000+0200}, author = {Zhu, Danfeng and Wang, Rui and Wang, Hui and Qian, Depei and Luan, Zhongzhi and Chu, Tianshu}, biburl = {https://www.bibsonomy.org/bibtex/228f4c3d42da800096a6803d2b514e2a1/dblp}, booktitle = {ICA3PP (1)}, crossref = {conf/ica3pp/2010-1}, editor = {Hsu, Ching-Hsien and Yang, Laurence Tianruo and Park, Jong Hyuk and Yeo, Sang-Soo}, ee = {https://doi.org/10.1007/978-3-642-13119-6_15}, interhash = {b6168d6afc986fde6279c99897da2d18}, intrahash = {28f4c3d42da800096a6803d2b514e2a1}, isbn = {978-3-642-13118-9}, keywords = {dblp}, pages = {174-185}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-05-15T17:47:50.000+0200}, title = {A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor.}, url = {http://dblp.uni-trier.de/db/conf/ica3pp/ica3pp2010-1.html#ZhuWWQLC10}, volume = 6081, year = 2010 }