%0 Journal Article %1 journals/jssc/VessalS04 %A Vessal, Farhang %A Salama, C. André T. %D 2004 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 238-241 %T An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology. %U http://dblp.uni-trier.de/db/journals/jssc/jssc39.html#VessalS04 %V 39

@article{journals/jssc/VessalS04, added-at = {2022-04-22T00:00:00.000+0200}, author = {Vessal, Farhang and Salama, C. André T.}, biburl = {https://www.bibsonomy.org/bibtex/23c406cf6b9897e671783b116189541ab/dblp}, ee = {https://doi.org/10.1109/JSSC.2003.820867}, interhash = {bcc3c032f835d57aba52f1eebad52dce}, intrahash = {3c406cf6b9897e671783b116189541ab}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {238-241}, timestamp = {2024-04-08T10:43:34.000+0200}, title = {An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc39.html#VessalS04}, volume = 39, year = 2004 }