,
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.
Y. Kim, H. Kim, J. Choi, M. Ahn, D. Lee, S. Cho, D. Park, Y. Park, M. Jang, Y. Kim, J. Choi, S. Yoon, J. Jung, J. Park, J. Lee, D. Kwon, H. Cha, S. Cho, S. Kim, J. You, K. Kim, D. Kim, B. Kim, Y. Kim, J. Kim, S. Choi, C. Kim, B. Na, H. Choi, R. Oh, J. Ihm, S. Bae, N. Kim, и J. Lee.ISSCC, стр. 346-348. IEEE, (2021)
Метаданные
- ключ BibTeX
- conf/isscc/KimKCALCPPJKCYJ21
- тип записи
- inproceedings
- название книги
- ISSCC
- год
- 2021
- страницы
- 346-348
- издательство
- IEEE
- Перекрестная ссылка BibTeX
- conf/isscc/2021
- ee
- https://doi.org/10.1109/ISSCC42613.2021.9366050
- isbn
- 978-1-7281-9549-0
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2021.html#KimKCALCPPJKCYJ21
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%0 Conference Paper
%1 conf/isscc/KimKCALCPPJKCYJ21
%A Kim, Yong-Hun
%A Kim, Hyung-Jin
%A Choi, Jaemin
%A Ahn, Min-Su
%A Lee, Dongkeon
%A Cho, Seung-Hyun
%A Park, Dong-Yeon
%A Park, Young-Jae
%A Jang, Min-Soo
%A Kim, Yong-Jun
%A Choi, Jinyong
%A Yoon, Sung-Woo
%A Jung, Jae-Woo
%A Park, Jae-Koo
%A Lee, Jae-Woo
%A Kwon, Dae-Hyun
%A Cha, Hyung-Seok
%A Cho, Si-Hyeong
%A Kim, Seong-Hoon
%A You, Jihwa
%A Kim, Kyoung-Ho
%A Kim, Dae-Hyun
%A Kim, Byung-Cheol
%A Kim, Young-Kwan
%A Kim, Jun-Ho
%A Choi, Seouk-Kyu
%A Kim, Chanyoung
%A Na, Byongwook
%A Choi, Hye-In
%A Oh, Reum
%A Ihm, Jeong-Don
%A Bae, Seung-Jun
%A Kim, Nam Sung
%A Lee, Jung-Bae
%B ISSCC
%D 2021
%I IEEE
%K dblp
%P 346-348
%T 25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2021.html#KimKCALCPPJKCYJ21
%@ 978-1-7281-9549-0
@inproceedings{conf/isscc/KimKCALCPPJKCYJ21,
added-at = {2023-07-30T00:00:00.000+0200},
author = {Kim, Yong-Hun and Kim, Hyung-Jin and Choi, Jaemin and Ahn, Min-Su and Lee, Dongkeon and Cho, Seung-Hyun and Park, Dong-Yeon and Park, Young-Jae and Jang, Min-Soo and Kim, Yong-Jun and Choi, Jinyong and Yoon, Sung-Woo and Jung, Jae-Woo and Park, Jae-Koo and Lee, Jae-Woo and Kwon, Dae-Hyun and Cha, Hyung-Seok and Cho, Si-Hyeong and Kim, Seong-Hoon and You, Jihwa and Kim, Kyoung-Ho and Kim, Dae-Hyun and Kim, Byung-Cheol and Kim, Young-Kwan and Kim, Jun-Ho and Choi, Seouk-Kyu and Kim, Chanyoung and Na, Byongwook and Choi, Hye-In and Oh, Reum and Ihm, Jeong-Don and Bae, Seung-Jun and Kim, Nam Sung and Lee, Jung-Bae},
biburl = {https://www.bibsonomy.org/bibtex/25cd35bcb67f46c9128e70f2570a6254b/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2021},
ee = {https://doi.org/10.1109/ISSCC42613.2021.9366050},
interhash = {bcfedef08363f58cc54638847c1650cf},
intrahash = {5cd35bcb67f46c9128e70f2570a6254b},
isbn = {978-1-7281-9549-0},
keywords = {dblp},
pages = {346-348},
publisher = {IEEE},
timestamp = {2024-04-09T20:43:12.000+0200},
title = {25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2021.html#KimKCALCPPJKCYJ21},
year = 2021
}