%0 Conference Paper %1 conf/sips/WarisWLL19 %A Waris, Haroon %A Wang, Chenghua %A Liu, Weiqiang %A Lombardi, Fabrizio %B SiPS %D 2019 %I IEEE %K dblp %P 13-18 %T Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication. %U http://dblp.uni-trier.de/db/conf/sips/sips2019.html#WarisWLL19 %@ 978-1-7281-1927-4

@inproceedings{conf/sips/WarisWLL19, added-at = {2023-02-22T00:00:00.000+0100}, author = {Waris, Haroon and Wang, Chenghua and Liu, Weiqiang and Lombardi, Fabrizio}, biburl = {https://www.bibsonomy.org/bibtex/29549bd1289d1cc6a829fb84546323a68/dblp}, booktitle = {SiPS}, crossref = {conf/sips/2019}, ee = {https://doi.org/10.1109/SiPS47522.2019.9020404}, interhash = {c00fb5201353947b1a2220b096716875}, intrahash = {9549bd1289d1cc6a829fb84546323a68}, isbn = {978-1-7281-1927-4}, keywords = {dblp}, pages = {13-18}, publisher = {IEEE}, timestamp = {2024-04-10T18:08:19.000+0200}, title = {Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication.}, url = {http://dblp.uni-trier.de/db/conf/sips/sips2019.html#WarisWLL19}, year = 2019 }