%0 Journal Article %1 journals/jssc/HuangCG15 %A Huang, Sui %A Cao, Jun %A Green, Michael M. %D 2015 %J IEEE J. Solid State Circuits %K dblp %N 9 %P 2048-2060 %T An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#HuangCG15 %V 50

@article{journals/jssc/HuangCG15, added-at = {2022-04-05T00:00:00.000+0200}, author = {Huang, Sui and Cao, Jun and Green, Michael M.}, biburl = {https://www.bibsonomy.org/bibtex/2f97aff766c59498f096561a05886fdca/dblp}, ee = {https://doi.org/10.1109/JSSC.2015.2427332}, interhash = {c46b3c1d27d82aee5f01399da4e25081}, intrahash = {f97aff766c59498f096561a05886fdca}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 9, pages = {2048-2060}, timestamp = {2024-04-08T10:44:11.000+0200}, title = {An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#HuangCG15}, volume = 50, year = 2015 }