%0 Conference Paper %1 conf/islped/NakataOKY10 %A Nakata, Yohei %A Okumura, Shunsuke %A Kawaguchi, Hiroshi %A Yoshimoto, Masahiko %B ISLPED %D 2010 %E Oklobdzija, Vojin G. %E Pangle, Barry %E Chang, Naehyuck %E Shanbhag, Naresh R. %E Kim, Chris H. %I ACM %K dblp %P 219-224 %T 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. %U http://dblp.uni-trier.de/db/conf/islped/islped2010.html#NakataOKY10 %@ 978-1-4503-0146-6

@inproceedings{conf/islped/NakataOKY10, added-at = {2024-03-11T00:00:00.000+0100}, author = {Nakata, Yohei and Okumura, Shunsuke and Kawaguchi, Hiroshi and Yoshimoto, Masahiko}, biburl = {https://www.bibsonomy.org/bibtex/2c627a37cc2a2de10567dd4377256d841/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2010}, editor = {Oklobdzija, Vojin G. and Pangle, Barry and Chang, Naehyuck and Shanbhag, Naresh R. and Kim, Chris H.}, ee = {https://doi.org/10.1145/1840845.1840888}, interhash = {caa483c6cc138e181c3fa9ab535fbdb6}, intrahash = {c627a37cc2a2de10567dd4377256d841}, isbn = {978-1-4503-0146-6}, keywords = {dblp}, pages = {219-224}, publisher = {ACM}, timestamp = {2024-04-10T21:21:35.000+0200}, title = {0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2010.html#NakataOKY10}, year = 2010 }