%0 Journal Article %1 journals/tcad/ParkM92 %A Park, Eun Sei %A Mercer, M. Ray %D 1992 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 7 %P 926-938 %T An efficient delay test generation system for combinational logic circuits. %U http://dblp.uni-trier.de/db/journals/tcad/tcad11.html#ParkM92 %V 11

@article{journals/tcad/ParkM92, added-at = {2020-09-24T00:00:00.000+0200}, author = {Park, Eun Sei and Mercer, M. Ray}, biburl = {https://www.bibsonomy.org/bibtex/286a455105509c922bdcaeb32d64f19ad/dblp}, ee = {https://doi.org/10.1109/43.144857}, interhash = {1ccaa72d3f0b8fe1d879fd1910c60e7c}, intrahash = {86a455105509c922bdcaeb32d64f19ad}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 7, pages = {926-938}, timestamp = {2020-09-25T11:44:57.000+0200}, title = {An efficient delay test generation system for combinational logic circuits.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad11.html#ParkM92}, volume = 11, year = 1992 }