%0 Journal Article %1 journals/jssc/OkudaNSNM00 %A Okuda, Takashi %A Naritake, Isao %A Sugibayashi, Tadahiko %A Nakajima, Yuji %A Murotani, Tatsunori %D 2000 %J IEEE J. Solid State Circuits %K dblp %N 8 %P 1153-1158 %T A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor. %U http://dblp.uni-trier.de/db/journals/jssc/jssc35.html#OkudaNSNM00 %V 35

@article{journals/jssc/OkudaNSNM00, added-at = {2022-04-08T00:00:00.000+0200}, author = {Okuda, Takashi and Naritake, Isao and Sugibayashi, Tadahiko and Nakajima, Yuji and Murotani, Tatsunori}, biburl = {https://www.bibsonomy.org/bibtex/2849e09895c82fb246eeddb241aca9995/dblp}, ee = {https://doi.org/10.1109/4.859504}, interhash = {cd507d1d8c29bf81369a1792b23e64d5}, intrahash = {849e09895c82fb246eeddb241aca9995}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 8, pages = {1153-1158}, timestamp = {2024-04-08T10:42:46.000+0200}, title = {A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc35.html#OkudaNSNM00}, volume = 35, year = 2000 }