%0 Conference Paper %1 conf/vlsi-dat/ChenJWHWLW18 %A Chen, Yung-Chih %A Ji, Wei-An %A Wang, Chih-Chung %A Huang, Ching-Yi %A Wu, Chia-Cheng %A Lin, Chia-Chun %A Wang, Chun-Yao %B VLSI-DAT %D 2018 %I IEEE %K dblp %P 1-4 %T Using range-equivalent circuits for facilitating bounded sequential equivalence checking. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2018.html#ChenJWHWLW18 %@ 978-1-5386-4260-3

@inproceedings{conf/vlsi-dat/ChenJWHWLW18, added-at = {2018-06-13T00:00:00.000+0200}, author = {Chen, Yung-Chih and Ji, Wei-An and Wang, Chih-Chung and Huang, Ching-Yi and Wu, Chia-Cheng and Lin, Chia-Chun and Wang, Chun-Yao}, biburl = {https://www.bibsonomy.org/bibtex/2c3d6b3a71ff7ce61c82a9c34e20db4c7/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2018}, ee = {https://doi.org/10.1109/VLSI-DAT.2018.8373231}, interhash = {cf642936887260747b1ff82f07f374f0}, intrahash = {c3d6b3a71ff7ce61c82a9c34e20db4c7}, isbn = {978-1-5386-4260-3}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2018-06-14T11:37:37.000+0200}, title = {Using range-equivalent circuits for facilitating bounded sequential equivalence checking.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2018.html#ChenJWHWLW18}, year = 2018 }