%0 Journal Article %1 journals/ieiceee/VijayakumarK14 %A Vijayakumar, S. %A Korah, Reeba %D 2014 %J IEICE Electron. Express %K dblp %N 6 %P 20140109 %T Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier. %U http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee11.html#VijayakumarK14 %V 11

@article{journals/ieiceee/VijayakumarK14, added-at = {2021-10-14T00:00:00.000+0200}, author = {Vijayakumar, S. and Korah, Reeba}, biburl = {https://www.bibsonomy.org/bibtex/2465a073563a5564919bb4e0e6d782a1b/dblp}, ee = {https://doi.org/10.1587/elex.11.20140109}, interhash = {d3073a8e50ce731d9e07232eb5e50981}, intrahash = {465a073563a5564919bb4e0e6d782a1b}, journal = {IEICE Electron. Express}, keywords = {dblp}, number = 6, pages = 20140109, timestamp = {2024-04-09T06:51:13.000+0200}, title = {Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier.}, url = {http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee11.html#VijayakumarK14}, volume = 11, year = 2014 }