%0 Journal Article %1 journals/npl/LuoWLHC18 %A Luo, Yuling %A Wan, Lei %A Liu, Junxiu %A Harkin, Jim %A Cao, Yi %D 2018 %J Neural Process. Lett. %K dblp %N 3 %P 1777-1788 %T An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations. %U http://dblp.uni-trier.de/db/journals/npl/npl48.html#LuoWLHC18 %V 48

@article{journals/npl/LuoWLHC18, added-at = {2023-08-28T00:00:00.000+0200}, author = {Luo, Yuling and Wan, Lei and Liu, Junxiu and Harkin, Jim and Cao, Yi}, biburl = {https://www.bibsonomy.org/bibtex/2b0bcc6164cfc46a00695be692b38fb5b/dblp}, ee = {https://www.wikidata.org/entity/Q115146140}, interhash = {d6d27884e66898be0600705514c845f0}, intrahash = {b0bcc6164cfc46a00695be692b38fb5b}, journal = {Neural Process. Lett.}, keywords = {dblp}, number = 3, pages = {1777-1788}, timestamp = {2024-04-08T14:51:24.000+0200}, title = {An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations.}, url = {http://dblp.uni-trier.de/db/journals/npl/npl48.html#LuoWLHC18}, volume = 48, year = 2018 }