%0 Journal Article %1 journals/tcasI/JingYYH22 %A Jing, Zhaokun %A Yan, Bonan %A Yang, Yuchao %A Huang, Ru %D 2022 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 10 %P 4028-4041 %T VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators. %U http://dblp.uni-trier.de/db/journals/tcasI/tcasI69.html#JingYYH22 %V 69

@article{journals/tcasI/JingYYH22, added-at = {2024-06-03T00:00:00.000+0200}, author = {Jing, Zhaokun and Yan, Bonan and Yang, Yuchao and Huang, Ru}, biburl = {https://www.bibsonomy.org/bibtex/2ee3c96c22df569de9a38aaec0e853d18/dblp}, ee = {https://doi.org/10.1109/TCSI.2022.3186024}, interhash = {d94ee6db32e430119c130cdaa575ed85}, intrahash = {ee3c96c22df569de9a38aaec0e853d18}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 10, pages = {4028-4041}, timestamp = {2024-06-10T07:03:10.000+0200}, title = {VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators.}, url = {http://dblp.uni-trier.de/db/journals/tcasI/tcasI69.html#JingYYH22}, volume = 69, year = 2022 }