%0 Conference Paper %1 conf/aspdac/ChenHSYW13 %A Chen, Shin-Shiun %A Hsu, Chun-Kai %A Shih, Hsiu-Chuan %A Yeh, Jen-Chieh %A Wu, Cheng-Wen %B ASP-DAC %D 2013 %I IEEE %K dblp %P 429-434 %T Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#ChenHSYW13 %@ 978-1-4673-3029-9

@inproceedings{conf/aspdac/ChenHSYW13, added-at = {2023-09-30T00:00:00.000+0200}, author = {Chen, Shin-Shiun and Hsu, Chun-Kai and Shih, Hsiu-Chuan and Yeh, Jen-Chieh and Wu, Cheng-Wen}, biburl = {https://www.bibsonomy.org/bibtex/2426d0c6b2351634e6656acc425952385/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2013}, ee = {https://doi.org/10.1109/ASPDAC.2013.6509634}, interhash = {db6f8fc7ed915df123b4e16b3eadbba9}, intrahash = {426d0c6b2351634e6656acc425952385}, isbn = {978-1-4673-3029-9}, keywords = {dblp}, pages = {429-434}, publisher = {IEEE}, timestamp = {2024-04-10T04:16:21.000+0200}, title = {Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#ChenHSYW13}, year = 2013 }