%0 Journal Article %1 journals/jssc/WangBHKNWZZB10 %A Wang, Yih %A Bhattacharya, Uddalak %A Hamzaoglu, Fatih %A Kolar, Pramod %A Ng, Yong-Gee %A Wei, Liqiong %A Zhang, Ying %A Zhang, Kevin %A Bohr, Mark %D 2010 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 103-110 %T A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. %U http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#WangBHKNWZZB10 %V 45

@article{journals/jssc/WangBHKNWZZB10, added-at = {2021-10-14T00:00:00.000+0200}, author = {Wang, Yih and Bhattacharya, Uddalak and Hamzaoglu, Fatih and Kolar, Pramod and Ng, Yong-Gee and Wei, Liqiong and Zhang, Ying and Zhang, Kevin and Bohr, Mark}, biburl = {https://www.bibsonomy.org/bibtex/26840faa31dc424c9b8f9a2989db51380/dblp}, ee = {https://doi.org/10.1109/JSSC.2009.2034082}, interhash = {dd7cfb4c31ade847f4568843c79db687}, intrahash = {6840faa31dc424c9b8f9a2989db51380}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {103-110}, timestamp = {2024-04-08T10:43:43.000+0200}, title = {A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#WangBHKNWZZB10}, volume = 45, year = 2010 }