%0 Journal Article %1 journals/tvlsi/VerplaetseSC01 %A Verplaetse, Peter %A Stroobandt, Dirk %A Campenhout, Jan M. Van %D 2001 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 6 %P 938-942 %T A stochastic model for the interconnection topology of digital circuits. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi9.html#VerplaetseSC01 %V 9

@article{journals/tvlsi/VerplaetseSC01, added-at = {2020-03-11T00:00:00.000+0100}, author = {Verplaetse, Peter and Stroobandt, Dirk and Campenhout, Jan M. Van}, biburl = {https://www.bibsonomy.org/bibtex/288f87529cb4980c5a6e158d3da16e622/dblp}, ee = {https://doi.org/10.1109/92.974907}, interhash = {dee6f4f6ed4590261bf361e9cee00b78}, intrahash = {88f87529cb4980c5a6e158d3da16e622}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 6, pages = {938-942}, timestamp = {2020-03-12T11:45:55.000+0100}, title = {A stochastic model for the interconnection topology of digital circuits.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi9.html#VerplaetseSC01}, volume = 9, year = 2001 }