%0 Journal Article %1 journals/ieicet/SuzukiYHSAY05 %A Suzuki, Toshikazu %A Yamagami, Yoshinobu %A Hatanaka, Ichiro %A Shibayama, Akinori %A Akamatsu, Hironori %A Yamauchi, Hiroyuki %D 2005 %J IEICE Trans. Electron. %K dblp %N 4 %P 630-638 %T 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet88c.html#SuzukiYHSAY05 %V 88-C

@article{journals/ieicet/SuzukiYHSAY05, added-at = {2024-02-05T00:00:00.000+0100}, author = {Suzuki, Toshikazu and Yamagami, Yoshinobu and Hatanaka, Ichiro and Shibayama, Akinori and Akamatsu, Hironori and Yamauchi, Hiroyuki}, biburl = {https://www.bibsonomy.org/bibtex/23a8e480141e02188946de9e20a5a68a1/dblp}, ee = {https://doi.org/10.1093/ietele/e88-c.4.630}, interhash = {e19834599e2349944498c114481a2924}, intrahash = {3a8e480141e02188946de9e20a5a68a1}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 4, pages = {630-638}, timestamp = {2024-04-08T15:50:03.000+0200}, title = {0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet88c.html#SuzukiYHSAY05}, volume = {88-C}, year = 2005 }