%0 Conference Paper %1 conf/glvlsi/ZhouZSWZ13 %A Zhou, Yi %A Zhang, Chao %A Sun, Guangyu %A Wang, Kun %A Zhang, Yu %B ACM Great Lakes Symposium on VLSI %D 2013 %E Ayala, José Luis %E Jones, Alex K. %E Madden, Patrick H. %E Coskun, Ayse K. %I ACM %K dblp %P 143-148 %T Asymmetric-access aware optimization for STT-RAM caches with process variations. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2013.html#ZhouZSWZ13 %@ 978-1-4503-2032-0

@inproceedings{conf/glvlsi/ZhouZSWZ13, added-at = {2019-05-18T00:00:00.000+0200}, author = {Zhou, Yi and Zhang, Chao and Sun, Guangyu and Wang, Kun and Zhang, Yu}, biburl = {https://www.bibsonomy.org/bibtex/2bc43855745c09d670931579a7ee233d4/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2013}, editor = {Ayala, José Luis and Jones, Alex K. and Madden, Patrick H. and Coskun, Ayse K.}, ee = {https://doi.org/10.1145/2483028.2483079}, interhash = {e2b6618ad76ae4af567f9492868fe8ac}, intrahash = {bc43855745c09d670931579a7ee233d4}, isbn = {978-1-4503-2032-0}, keywords = {dblp}, pages = {143-148}, publisher = {ACM}, timestamp = {2019-07-24T11:38:00.000+0200}, title = {Asymmetric-access aware optimization for STT-RAM caches with process variations.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2013.html#ZhouZSWZ13}, year = 2013 }