%0 Journal Article %1 journals/tcad/ZhuW97 %A Zhu, Kai %A Wong, Martin D. F. %D 1997 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 4 %P 376-385 %T Clock skew minimization during FPGA placement. %U http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#ZhuW97 %V 16

@article{journals/tcad/ZhuW97, added-at = {2022-10-02T00:00:00.000+0200}, author = {Zhu, Kai and Wong, Martin D. F.}, biburl = {https://www.bibsonomy.org/bibtex/23c7411b5959dde6b7aaa689232e1e704/dblp}, ee = {https://doi.org/10.1109/43.602474}, interhash = {e72af64f6ed01991522c61ccdffc857a}, intrahash = {3c7411b5959dde6b7aaa689232e1e704}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 4, pages = {376-385}, timestamp = {2024-04-08T19:46:35.000+0200}, title = {Clock skew minimization during FPGA placement.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#ZhuW97}, volume = 16, year = 1997 }