%0 Journal Article %1 journals/cee/HeWZ09 %A He, Min %A Wu, Xiaolong %A Zheng, Si-Qing %D 2009 %J Comput. Electr. Eng. %K dblp %N 6 %P 951-965 %T An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system. %U http://dblp.uni-trier.de/db/journals/cee/cee35.html#HeWZ09 %V 35

@article{journals/cee/HeWZ09, added-at = {2020-02-19T00:00:00.000+0100}, author = {He, Min and Wu, Xiaolong and Zheng, Si-Qing}, biburl = {https://www.bibsonomy.org/bibtex/29ac20d38667c0f6c6673fa9ccc644e70/dblp}, ee = {https://doi.org/10.1016/j.compeleceng.2008.11.020}, interhash = {ea00c8dc34844d474b6befe7f6e36538}, intrahash = {9ac20d38667c0f6c6673fa9ccc644e70}, journal = {Comput. Electr. Eng.}, keywords = {dblp}, number = 6, pages = {951-965}, timestamp = {2020-02-20T12:04:38.000+0100}, title = {An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system.}, url = {http://dblp.uni-trier.de/db/journals/cee/cee35.html#HeWZ09}, volume = 35, year = 2009 }