%0 Conference Paper %1 conf/vlsic/ChenKDBZ16 %A Chen, Zhanping %A Kulkarni, Sarvesh H. %A Dorgan, Vincent E. %A Bhattacharya, Uddalak %A Zhang, Kevin %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ChenKDBZ16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/ChenKDBZ16, added-at = {2023-02-06T00:00:00.000+0100}, author = {Chen, Zhanping and Kulkarni, Sarvesh H. and Dorgan, Vincent E. and Bhattacharya, Uddalak and Zhang, Kevin}, biburl = {https://www.bibsonomy.org/bibtex/24b365c186447bbea2ce7c1cca4906361/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {https://doi.org/10.1109/VLSIC.2016.7573506}, interhash = {ea40eb5457b06b82c22e1db813e0c03c}, intrahash = {4b365c186447bbea2ce7c1cca4906361}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-10T15:34:06.000+0200}, title = {A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ChenKDBZ16}, year = 2016 }