%0 Conference Paper %1 conf/asap/MeherP08 %A Meher, Pramod Kumar %A Patra, Jagdish Chandra %B ASAP %D 2008 %I IEEE Computer Society %K dblp %P 43-48 %T Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. %U http://dblp.uni-trier.de/db/conf/asap/asap2008.html#MeherP08 %@ 978-1-4244-1897-8

@inproceedings{conf/asap/MeherP08, added-at = {2023-03-24T00:00:00.000+0100}, author = {Meher, Pramod Kumar and Patra, Jagdish Chandra}, biburl = {https://www.bibsonomy.org/bibtex/2ed0be53836dddaa4fc7f23bdd0c49ae4/dblp}, booktitle = {ASAP}, crossref = {conf/asap/2008}, ee = {https://doi.ieeecomputersociety.org/10.1109/ASAP.2008.4580152}, interhash = {f3b4a76ea756bab31125812dd0419f3f}, intrahash = {ed0be53836dddaa4fc7f23bdd0c49ae4}, isbn = {978-1-4244-1897-8}, keywords = {dblp}, pages = {43-48}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T22:08:27.000+0200}, title = {Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform.}, url = {http://dblp.uni-trier.de/db/conf/asap/asap2008.html#MeherP08}, year = 2008 }