%0 Journal Article %1 journals/tcad/KimCY09 %A Kim, Myeongjin %A Chung, Eui-Young %A Yoon, Sungroh %D 2009 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 8 %P 1274-1278 %T High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation. %U http://dblp.uni-trier.de/db/journals/tcad/tcad28.html#KimCY09 %V 28

@article{journals/tcad/KimCY09, added-at = {2020-09-24T00:00:00.000+0200}, author = {Kim, Myeongjin and Chung, Eui-Young and Yoon, Sungroh}, biburl = {https://www.bibsonomy.org/bibtex/2088802c123b12817a81b47cc8050bfd4/dblp}, ee = {https://doi.org/10.1109/TCAD.2009.2020716}, interhash = {f4d12dc71e73b81a906806ed74c4f63c}, intrahash = {088802c123b12817a81b47cc8050bfd4}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 8, pages = {1274-1278}, timestamp = {2020-09-25T11:50:32.000+0200}, title = {High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad28.html#KimCY09}, volume = 28, year = 2009 }