%0 Journal Article %1 journals/tcad/ZhongJ05 %A Zhong, Lin %A Jha, Niraj K. %D 2005 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 3 %P 336-351 %T Interconnect-aware low-power high-level synthesis. %U http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#ZhongJ05 %V 24

@article{journals/tcad/ZhongJ05, added-at = {2020-09-24T00:00:00.000+0200}, author = {Zhong, Lin and Jha, Niraj K.}, biburl = {https://www.bibsonomy.org/bibtex/22bc0a3b488a22948af8f384c1b70ff4b/dblp}, ee = {https://doi.org/10.1109/TCAD.2004.842820}, interhash = {f70a485332727fa6ad92f4610fafeaf3}, intrahash = {2bc0a3b488a22948af8f384c1b70ff4b}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 3, pages = {336-351}, timestamp = {2020-09-25T11:48:41.000+0200}, title = {Interconnect-aware low-power high-level synthesis.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#ZhongJ05}, volume = 24, year = 2005 }