%0 Conference Paper %1 zabolotny2010memory %A Zabolotny, Wojciech %B Proceedings of the SPIE %D 2010 %K DSP FPGA dual memory myown parallel port processing %P 77451E-77451E-8 %T Dual port memory based parallel programmable architecture for DSP in FPGA %U http://dx.doi.org/10.1117/12.872828 %V 7745 %X This document presents a proposal of a new architecture for implementation of Digital Signal Processing (DSP) algorithms in Field-Programmable Gate Array (FPGA). The proposed approach uses the dual port memory for fast exchange of information between the processing units implemented in the FPGA. The special, parametrized scheme of interconnections between processing units has been also proposed, which allows to synthesize DSP system with customized number of processing units. The proposed interconnections scheme provides possibility to quickly transfer the data between processing units, at reasonable consumption of routing resources. The proposed architecture has been tested in simulations, and synthesized for real FPGA chips to verify its correctness.

@inproceedings{zabolotny2010memory, abstract = {This document presents a proposal of a new architecture for implementation of Digital Signal Processing (DSP) algorithms in Field-Programmable Gate Array (FPGA). The proposed approach uses the dual port memory for fast exchange of information between the processing units implemented in the FPGA. The special, parametrized scheme of interconnections between processing units has been also proposed, which allows to synthesize DSP system with customized number of processing units. The proposed interconnections scheme provides possibility to quickly transfer the data between processing units, at reasonable consumption of routing resources. The proposed architecture has been tested in simulations, and synthesized for real FPGA chips to verify its correctness. }, added-at = {2012-09-07T20:51:28.000+0200}, author = {Zabolotny, Wojciech}, biburl = {https://www.bibsonomy.org/bibtex/2317bfd36c56cc43698b6ecb527da6327/wzab}, booktitle = {Proceedings of the SPIE}, interhash = {200cee2bd14841d5554efabf08a8a3c4}, intrahash = {317bfd36c56cc43698b6ecb527da6327}, keywords = {DSP FPGA dual memory myown parallel port processing}, pages = {77451E-77451E-8}, timestamp = {2012-09-07T20:51:28.000+0200}, title = {Dual port memory based parallel programmable architecture for DSP in FPGA}, url = {http://dx.doi.org/10.1117/12.872828}, volume = 7745, year = 2010 }