%0 Conference Paper %1 4762407 %A Meeuws, R. %A Sigdel, K. %A Yankova, Y. %A Bertels, K. %B ICECE Technology, 2008. FPT 2008. International Conference on %D 2008 %K delft hardware myown prediction quantitative %P 317 -320 %R 10.1109/FPT.2008.4762407 %T High level quantitative interconnect estimation for Early Design Space Exploration %X In this paper, we present an approach for prediction of interconnect resources at the early stages of design. This approach was developed as an extension to the Quipu multi-dimensional quantitative prediction model for early design space exploration. Quipu is a part of the Delft Workbench project, a semi-automatic tool platform supporting integrated hardware-software co-design for heterogeneous computing systems. Because of the highly iterative nature of design in such tool platforms, fast and early estimates of hardware properties are required. One aspect of particular importance is the utilization of interconnect resources, which has increased with designs becoming larger, even to the point where some designs are no longer routable. We establish a method of estimating interconnect from a C-level description using partial least squares regression (PLSR) and software complexity metrics (SCM) for use in the Delft Workbench tool platform. We show that our approach can make predictions with an expected error of 31.6%.

@inproceedings{4762407, abstract = {In this paper, we present an approach for prediction of interconnect resources at the early stages of design. This approach was developed as an extension to the Quipu multi-dimensional quantitative prediction model for early design space exploration. Quipu is a part of the Delft Workbench project, a semi-automatic tool platform supporting integrated hardware-software co-design for heterogeneous computing systems. Because of the highly iterative nature of design in such tool platforms, fast and early estimates of hardware properties are required. One aspect of particular importance is the utilization of interconnect resources, which has increased with designs becoming larger, even to the point where some designs are no longer routable. We establish a method of estimating interconnect from a C-level description using partial least squares regression (PLSR) and software complexity metrics (SCM) for use in the Delft Workbench tool platform. We show that our approach can make predictions with an expected error of 31.6%.}, added-at = {2010-08-23T14:31:38.000+0200}, author = {Meeuws, R. and Sigdel, K. and Yankova, Y. and Bertels, K.}, biburl = {https://www.bibsonomy.org/bibtex/20517f0ce5f391b5334b27644340c9f0c/roelmeeuws}, booktitle = {ICECE Technology, 2008. FPT 2008. International Conference on}, doi = {10.1109/FPT.2008.4762407}, interhash = {3478a766c5c8dc7fb69cf30a18fb97ae}, intrahash = {0517f0ce5f391b5334b27644340c9f0c}, keywords = {delft hardware myown prediction quantitative}, month = {dec.}, pages = {317 -320}, timestamp = {2012-07-10T18:07:36.000+0200}, title = {High level quantitative interconnect estimation for Early Design Space Exploration}, year = 2008 }