%0 Conference Paper %1 conf/dac/ReddyAJ84 %A Reddy, Sudhakar M. %A Agrawal, Vishwani D. %A Jain, Sunil K. %B DAC %D 1984 %E Lambert, Patricia H. %E Ofek, Hillel %E O'Neill, Lawrence A. %E Pistilli, Pat O. %E Losleben, Paul %E Nash, J. Daniel %E Shaklee, Dennis W. %E Preas, Bryan T. %E Lerman, Harvey N. %I ACM/IEEE %K dblp %P 504-509 %T A gate level model for CMOS combinational logic circuits with application to fault detection. %U http://dblp.uni-trier.de/db/conf/dac/dac1984.html#ReddyAJ84 %@ 0-8186-0542-1

@inproceedings{conf/dac/ReddyAJ84, added-at = {2012-03-01T00:00:00.000+0100}, author = {Reddy, Sudhakar M. and Agrawal, Vishwani D. and Jain, Sunil K.}, biburl = {https://www.bibsonomy.org/bibtex/21352f727233e8c759b08f34dc641dfbe/dblp}, booktitle = {DAC}, crossref = {conf/dac/1984}, editor = {Lambert, Patricia H. and Ofek, Hillel and O'Neill, Lawrence A. and Pistilli, Pat O. and Losleben, Paul and Nash, J. Daniel and Shaklee, Dennis W. and Preas, Bryan T. and Lerman, Harvey N.}, ee = {http://dl.acm.org/citation.cfm?id=800846}, interhash = {3d3702d917afca5e6a2020abdb8c3a9c}, intrahash = {1352f727233e8c759b08f34dc641dfbe}, isbn = {0-8186-0542-1}, keywords = {dblp}, pages = {504-509}, publisher = {ACM/IEEE}, timestamp = {2024-04-10T01:57:22.000+0200}, title = {A gate level model for CMOS combinational logic circuits with application to fault detection.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac1984.html#ReddyAJ84}, year = 1984 }