%0 Conference Paper %1 yu2011 %A Yu, Qiaoyan %A Zhang, Meilin %A Ampadu, P. %B Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on %D 2011 %K exploring fault noc redundancy tolerant %P 105-112 %T Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration %U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5948551 %X We exploit the inherent information redundancy in the control path of Networks-on-Chip (NoCs) routers to manage transient errors, preventing packet loss and misrouting. Unlike fault-tolerant routing, our method does not drop packets when faults occur in routers and thus does not increase the burden on neighboring routers. Unlike the NoC interconnect links, the routing operation is nonlinear and standard error control coding methods cannot be used. Instead, our method exploits existing information redundancy in the router, significantly reducing the area overhead and power consumption compared to triple-modular redundancy (TMR). An analytical reliability model of our method is provided, including parameters such as circuit size, different error rates for logic gates and registers, and the location of a faulty element. Compared to TMR, the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total power and area by 43% and 64%, respectively. Simulations performed on a 4×4 NoC show that our method reduces the average latency by up to 90% and 12% over no-protection and TMR methods, respectively.

@inproceedings{yu2011, abstract = {We exploit the inherent information redundancy in the control path of Networks-on-Chip (NoCs) routers to manage transient errors, preventing packet loss and misrouting. Unlike fault-tolerant routing, our method does not drop packets when faults occur in routers and thus does not increase the burden on neighboring routers. Unlike the NoC interconnect links, the routing operation is nonlinear and standard error control coding methods cannot be used. Instead, our method exploits existing information redundancy in the router, significantly reducing the area overhead and power consumption compared to triple-modular redundancy (TMR). An analytical reliability model of our method is provided, including parameters such as circuit size, different error rates for logic gates and registers, and the location of a faulty element. Compared to TMR, the proposed method improves the arbiter reliability by two orders of magnitude while reducing the total power and area by 43% and 64%, respectively. Simulations performed on a 4×4 NoC show that our method reduces the average latency by up to 90% and 12% over no-protection and TMR methods, respectively.}, added-at = {2013-07-15T17:48:06.000+0200}, author = {Yu, Qiaoyan and Zhang, Meilin and Ampadu, P.}, biburl = {https://www.bibsonomy.org/bibtex/21a8c016295d11c3c8f338c584f3a118e/eberle18}, booktitle = {Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on}, description = {IEEE Xplore - Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration}, interhash = {176ee1691a9c070991d6ae0d6aaa847b}, intrahash = {1a8c016295d11c3c8f338c584f3a118e}, keywords = {exploring fault noc redundancy tolerant}, pages = {105-112}, timestamp = {2013-07-15T17:48:07.000+0200}, title = {Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5948551}, year = 2011 }