%0 Conference Paper %1 conf/isvlsi/BerthelotN06 %A Berthelot, Florent %A Nouvel, Fabienne %B ISVLSI %D 2006 %I IEEE Computer Society %K dblp %P 436-437 %T Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2006.html#BerthelotN06 %@ 0-7695-2533-4

@inproceedings{conf/isvlsi/BerthelotN06, added-at = {2023-03-24T00:00:00.000+0100}, author = {Berthelot, Florent and Nouvel, Fabienne}, biburl = {https://www.bibsonomy.org/bibtex/2236d3d31847946801c84bce1f319b455/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.71}, interhash = {ce7c21048fbd11f3c60f081b5d74bed8}, intrahash = {236d3d31847946801c84bce1f319b455}, isbn = {0-7695-2533-4}, keywords = {dblp}, pages = {436-437}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T11:06:14.000+0200}, title = {Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2006.html#BerthelotN06}, year = 2006 }