PERFORMANCE ENHANCEMENT WITH SPECULATIVE-
TRACEC APPINGATD IFFERENT PIPELINESTAGES IN SIMULTANEOUS MULTI-THREADING PROCESSORS
Computer Applications: An International Journal (CAIJ),, 3 (4):
1-19 (11/2016 2016)Abstract
Simultaneous Multi
-
Threading (SMT) processors improve system performance by allowing concu
rrent
execution of multiple in
dependent threads with sharing key datapath components and better utilization of
resources. Specu
lative execution allows modern processors to fetch continuously and reduce the delays of
control instructions. However, a significant amount of resources
is
usually wasted due to miss
-
speculation,
which could have been used by other valid instructions, and
such a waste is even more pronounced in an
SMT system. In order to minimize the waste of resources, a speculative trace capping technique 1 was
proposed to limit the number of speculative instructions in the system. In this paper, a thorough analysis is
given to investigate the trade
-
offs among applying this capping mechanism at different pipeline stages so as
to maximize its benefits. Our simulations show that the best choice can improve overall system throughput
by a very significant margin (up to 46%)
without sacrificing execution fairness among the threads.