design synchronous sequential logic circuits with
minimum number of logic gates is suggested. The
proposed method consists of four main stages. The first
stage is concerned with the use of genetic algorithms
(GA) for the state assignment problem to compute
optimal binary codes for each symbolic state and
construct the state transition table of finite state
machine (FSM). The second stage defines the subcircuits
required to achieve the desired functionality. The
third stage evaluates the subcircuits using extrinsic
Evolvable Hardware (EHW). During the fourth stage, the
final circuit is assembled. The obtained results
compare favourably against those produced by manual
methods and other methods based on heuristic
techniques.
%0 Journal Article
%1 ali:2004:GPEM
%A Ali, B.
%A Almaini, A. E. A.
%A Kalganova, T.
%D 2004
%J Genetic Programming and Evolvable Machines
%K algorithms, assignment circuits, evolvable genetic hardware, sequential state
%N 1
%R doi:10.1023/B:GENP.0000017009.11392.e2
%T Evolutionary Algorithms and Theirs Use in the Design
of Sequential Logic Circuits
%V 5
%X design synchronous sequential logic circuits with
minimum number of logic gates is suggested. The
proposed method consists of four main stages. The first
stage is concerned with the use of genetic algorithms
(GA) for the state assignment problem to compute
optimal binary codes for each symbolic state and
construct the state transition table of finite state
machine (FSM). The second stage defines the subcircuits
required to achieve the desired functionality. The
third stage evaluates the subcircuits using extrinsic
Evolvable Hardware (EHW). During the fourth stage, the
final circuit is assembled. The obtained results
compare favourably against those produced by manual
methods and other methods based on heuristic
techniques.
@article{ali:2004:GPEM,
abstract = {design synchronous sequential logic circuits with
minimum number of logic gates is suggested. The
proposed method consists of four main stages. The first
stage is concerned with the use of genetic algorithms
(GA) for the state assignment problem to compute
optimal binary codes for each symbolic state and
construct the state transition table of finite state
machine (FSM). The second stage defines the subcircuits
required to achieve the desired functionality. The
third stage evaluates the subcircuits using extrinsic
Evolvable Hardware (EHW). During the fourth stage, the
final circuit is assembled. The obtained results
compare favourably against those produced by manual
methods and other methods based on heuristic
techniques.},
added-at = {2008-06-19T17:35:00.000+0200},
author = {Ali, B. and Almaini, A. E. A. and Kalganova, T.},
biburl = {https://www.bibsonomy.org/bibtex/23187af390b4b72ce4128dc1faf3a2aca/brazovayeye},
doi = {doi:10.1023/B:GENP.0000017009.11392.e2},
interhash = {6db02f5c9d6b431a0442c5a0df05e913},
intrahash = {3187af390b4b72ce4128dc1faf3a2aca},
issn = {1389-2576},
journal = {Genetic Programming and Evolvable Machines},
keywords = {algorithms, assignment circuits, evolvable genetic hardware, sequential state},
month = {March},
notes = {Article ID: 5264733},
number = 1,
timestamp = {2008-06-19T17:35:33.000+0200},
title = {Evolutionary Algorithms and Theirs Use in the Design
of Sequential Logic Circuits},
volume = 5,
year = 2004
}