%0 Conference Paper %1 conf/glvlsi/ShinoharaHLDYN11 %A Shinohara, Kota %A Hidaka, Mihoko %A Li, Jing %A Dong, Qing %A Yang, Bo %A Nakatake, Shigetoshi %B ACM Great Lakes Symposium on VLSI %D 2011 %E Atienza, David %E Xie, Yuan %E Ayala, José L. %E Stevens, Ken S. %I ACM %K dblp %P 247-252 %T Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2011.html#ShinoharaHLDYN11 %@ 978-1-4503-0667-6

@inproceedings{conf/glvlsi/ShinoharaHLDYN11, added-at = {2020-09-17T00:00:00.000+0200}, author = {Shinohara, Kota and Hidaka, Mihoko and Li, Jing and Dong, Qing and Yang, Bo and Nakatake, Shigetoshi}, biburl = {https://www.bibsonomy.org/bibtex/238bd7c476eda3779d46cdf954b23a8c3/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2011}, editor = {Atienza, David and Xie, Yuan and Ayala, José L. and Stevens, Ken S.}, ee = {https://doi.org/10.1145/1973009.1973059}, interhash = {656622e6b7cbf0971dd428acfdc15c75}, intrahash = {38bd7c476eda3779d46cdf954b23a8c3}, isbn = {978-1-4503-0667-6}, keywords = {dblp}, pages = {247-252}, publisher = {ACM}, timestamp = {2020-09-18T11:53:05.000+0200}, title = {Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2011.html#ShinoharaHLDYN11}, year = 2011 }