%0 Journal Article %1 journals/tcad/Schafer17 %A Schäfer, Benjamin Carrión %D 2017 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 1 %P 97-105 %T Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments. %U http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#Schafer17 %V 36

@article{journals/tcad/Schafer17, added-at = {2020-09-24T00:00:00.000+0200}, author = {Schäfer, Benjamin Carrión}, biburl = {https://www.bibsonomy.org/bibtex/242dafa85b068190bebc6252ff211da9c/dblp}, ee = {https://doi.org/10.1109/TCAD.2016.2550501}, interhash = {116ec3e21579f220767b4c832750e180}, intrahash = {42dafa85b068190bebc6252ff211da9c}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 1, pages = {97-105}, timestamp = {2020-09-25T11:47:56.000+0200}, title = {Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#Schafer17}, volume = 36, year = 2017 }