Review on Designing of Multi Bit Flip-Flop to Achieve Reduced Area in VLSI Design
Y. Bhole, and N. Thune. International Journal of Innovative Science and Modern Engineering (IJISME), 3 (9):
1-2(August 2015)
Abstract
In this paper, we have designed Multi-bit Flip-flop (MBFF) and made performance comparison over the Single-bit Flip-flop (SBFF) We can increase Flip flop performance by merging clock pulse. But increase in clock pulse means it will increases the area. So the Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop so it will reduce the area. The basic memory elements of designer considerations are Latch and flip flop. Optimizations in VLSI have been done on three factors: Area, Power and Timing (Speed). Area optimization means reducing the space of logic which occupy on the die. Memory elements play a vital role on Digital World but these elements consumes more area. Thus these elements can be designed using Multi-bit flip flop to reduce area.
%0 Journal Article
%1 noauthororeditor
%A Bhole, Yogita D.
%A Thune, N. N.
%D 2015
%E Kumar, Dr. Shiv
%J International Journal of Innovative Science and Modern Engineering (IJISME)
%K Clock Flip-flop Gate Latch Multi Single bit buffer delay flip flop flop. network
%N 9
%P 1-2
%T Review on Designing of Multi Bit Flip-Flop to Achieve Reduced Area in VLSI Design
%U https://www.ijisme.org/wp-content/uploads/papers/v3i9/I0920083915.pdf
%V 3
%X In this paper, we have designed Multi-bit Flip-flop (MBFF) and made performance comparison over the Single-bit Flip-flop (SBFF) We can increase Flip flop performance by merging clock pulse. But increase in clock pulse means it will increases the area. So the Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop so it will reduce the area. The basic memory elements of designer considerations are Latch and flip flop. Optimizations in VLSI have been done on three factors: Area, Power and Timing (Speed). Area optimization means reducing the space of logic which occupy on the die. Memory elements play a vital role on Digital World but these elements consumes more area. Thus these elements can be designed using Multi-bit flip flop to reduce area.
@article{noauthororeditor,
abstract = {In this paper, we have designed Multi-bit Flip-flop (MBFF) and made performance comparison over the Single-bit Flip-flop (SBFF) We can increase Flip flop performance by merging clock pulse. But increase in clock pulse means it will increases the area. So the Multi-bit Flip-flop is designed by single clock pulse and achieves same functionality like two single-bit Flip-flop so it will reduce the area. The basic memory elements of designer considerations are Latch and flip flop. Optimizations in VLSI have been done on three factors: Area, Power and Timing (Speed). Area optimization means reducing the space of logic which occupy on the die. Memory elements play a vital role on Digital World but these elements consumes more area. Thus these elements can be designed using Multi-bit flip flop to reduce area.},
added-at = {2021-09-18T12:38:19.000+0200},
author = {Bhole, Yogita D. and Thune, N. N.},
biburl = {https://www.bibsonomy.org/bibtex/25669a28f729a8fee900ea65697736118/ijisme_beiesp},
editor = {Kumar, Dr. Shiv},
interhash = {2b82e2a0b8e1f384e5bddd524d1cb04f},
intrahash = {5669a28f729a8fee900ea65697736118},
issn = {2347-6389},
journal = {International Journal of Innovative Science and Modern Engineering (IJISME)},
keywords = {Clock Flip-flop Gate Latch Multi Single bit buffer delay flip flop flop. network},
language = {En},
month = {August},
number = 9,
pages = {1-2},
timestamp = {2021-09-18T12:38:19.000+0200},
title = {Review on Designing of Multi Bit Flip-Flop to Achieve Reduced Area in VLSI Design},
url = {https://www.ijisme.org/wp-content/uploads/papers/v3i9/I0920083915.pdf},
volume = 3,
year = 2015
}