%0 Journal Article %1 nayaka2012performance %A Nayaka, Raja Jitendra %A Biradar, R. C. %D 2012 %J International Journal of Next-Generation Networks (IJNGN) %K 1/10/20/40/100 Ethernet FPGA Gigab IP LAN NGN Router SoC Switches and networks %N 3 %P 87 -99 %T HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKS %U http://airccse.org/journal/ijngn/current2012.html %V 4 %X As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA.

@article{nayaka2012performance, abstract = {As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA. }, added-at = {2018-04-27T14:14:02.000+0200}, author = {Nayaka, Raja Jitendra and Biradar, R. C.}, biburl = {https://www.bibsonomy.org/bibtex/2780ed1e2541e6a871141208ca55a7f15/ijfls}, interhash = {e12d46a6fc296e885231ce2c1e3fc661}, intrahash = {780ed1e2541e6a871141208ca55a7f15}, journal = {International Journal of Next-Generation Networks (IJNGN)}, keywords = {1/10/20/40/100 Ethernet FPGA Gigab IP LAN NGN Router SoC Switches and networks}, month = sep, number = 3, pages = {87 -99}, timestamp = {2018-04-27T14:14:02.000+0200}, title = {HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKS }, url = {http://airccse.org/journal/ijngn/current2012.html}, volume = 4, year = 2012 }