%0 Journal Article %1 journals/vlsisp/ArtesFARC13 %A Artés, Antonio %A Fasthuber, Robert %A Ayala, José Luis %A Raghavan, Praveen %A Catthoor, Francky %D 2013 %J J. Signal Process. Syst. %K dblp %N 1 %P 69-85 %T Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp72.html#ArtesFARC13 %V 72

@article{journals/vlsisp/ArtesFARC13, added-at = {2022-10-02T00:00:00.000+0200}, author = {Artés, Antonio and Fasthuber, Robert and Ayala, José Luis and Raghavan, Praveen and Catthoor, Francky}, biburl = {https://www.bibsonomy.org/bibtex/27e4b7befd8d1849cfdd99b36e05995e8/dblp}, ee = {https://doi.org/10.1007/s11265-013-0749-z}, interhash = {f5f03dc272663f3c0337cd7d4467a0c4}, intrahash = {7e4b7befd8d1849cfdd99b36e05995e8}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 1, pages = {69-85}, timestamp = {2024-04-09T03:12:22.000+0200}, title = {Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp72.html#ArtesFARC13}, volume = 72, year = 2013 }