A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. The main objective of this paper is to present the analysis of leakage components, comprehensive study & analysis of leakage components and to present different proposed leakage power reduction techniques
%0 Journal Article
%1 Tonk_2015
%A Tonk, Anu
%A Goyal, Shilpa
%D 2015
%I Auricle Technologies, Pvt., Ltd.
%J International Journal on Recent and Innovation Trends in Computing and Communication
%K CMOS Leakage Power Sub-threshold Threshold voltage
%N 2
%P 554--558
%R 10.17762/ijritcc2321-8169.150228
%T A Literature Review on Leakage and Power Reduction Techniques in CMOS VLSI Design
%U http://dx.doi.org/10.17762/ijritcc2321-8169.150228
%V 3
%X A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. The main objective of this paper is to present the analysis of leakage components, comprehensive study & analysis of leakage components and to present different proposed leakage power reduction techniques
@article{Tonk_2015,
abstract = {A rapid growth in semiconductor technology and increasing demand for portable devices powered up by battery has led the manufacturers to scale down the feature size, resulting reduced threshold voltage and thereby enabling integration of extremely complex functionality on a single chip. In CMOS circuits, increased sub-threshold leakage current refers static power dissipation is the result of low threshold voltage. For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers. According to ITRS (International technology road-map for semiconductors), leakage power is becoming a dominant part of total power consumption. To prolong the battery life of portable devices, leakage power reduction is the primary goal. The main objective of this paper is to present the analysis of leakage components, comprehensive study & analysis of leakage components and to present different proposed leakage power reduction techniques},
added-at = {2015-08-04T07:19:59.000+0200},
author = {Tonk, Anu and Goyal, Shilpa},
biburl = {https://www.bibsonomy.org/bibtex/289f68c27ac4ff156bf96d252f24ee07d/ijritcc},
doi = {10.17762/ijritcc2321-8169.150228},
interhash = {0781915b47fb7967c4cd20994bd149f2},
intrahash = {89f68c27ac4ff156bf96d252f24ee07d},
journal = {International Journal on Recent and Innovation Trends in Computing and Communication},
keywords = {CMOS Leakage Power Sub-threshold Threshold voltage},
month = {february},
number = 2,
pages = {554--558},
publisher = {Auricle Technologies, Pvt., Ltd.},
timestamp = {2015-08-04T07:19:59.000+0200},
title = {A Literature Review on Leakage and Power Reduction Techniques in {CMOS} {VLSI} Design},
url = {http://dx.doi.org/10.17762/ijritcc2321-8169.150228},
volume = 3,
year = 2015
}