%0 Conference Paper %1 Mendel2007Zdomain %A Mendel, Stefan %A Vogel, Christian %B Proceedings of the IEEE Norchip Conference 2007 %D 2007 %K adpll, all-digital, analysis, loops, model, phase-locked, pll, z-domain %T A z-domain model and analysis of phase-domain all-digital phase-locked loops %U http://dx.doi.org/10.1109/NORCHP.2007.4481030 %X In this paper a comprehensive z-domain model of all-digital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus reflects both, frequency and phase behavior. The system model is investigated in detail. Each component is described in form of its transfer function to obtain an overall input/output behavior for the frequency and the phase domain. Furthermore, the physical characteristics of the noise sources within the structure are studied and their effects on the phase noise of the PLL are determined. The system level model is independent of the actual implementation, however, the relation to an existing frequency synthesizer for wireless communications is discussed. Simulation results confirm the accurateness of the presented model with respect to the time and frequency behavior of the system.

@inproceedings{Mendel2007Zdomain, abstract = {In this paper a comprehensive z-domain model of all-digital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus reflects both, frequency and phase behavior. The system model is investigated in detail. Each component is described in form of its transfer function to obtain an overall input/output behavior for the frequency and the phase domain. Furthermore, the physical characteristics of the noise sources within the structure are studied and their effects on the phase noise of the PLL are determined. The system level model is independent of the actual implementation, however, the relation to an existing frequency synthesizer for wireless communications is discussed. Simulation results confirm the accurateness of the presented model with respect to the time and frequency behavior of the system.}, added-at = {2009-02-06T11:50:52.000+0100}, author = {Mendel, Stefan and Vogel, Christian}, biburl = {https://www.bibsonomy.org/bibtex/29cd440c73ae8f2c9fb24aca98b388d3c/peteru}, booktitle = {Proceedings of the {IEEE} Norchip Conference 2007}, interhash = {33fb31fe4f53d5b189fab0ddc72b2447}, intrahash = {9cd440c73ae8f2c9fb24aca98b388d3c}, keywords = {adpll, all-digital, analysis, loops, model, phase-locked, pll, z-domain}, month = {November}, timestamp = {2009-02-06T11:50:52.000+0100}, title = {A z-domain model and analysis of phase-domain all-digital phase-locked loops}, url = {http://dx.doi.org/10.1109/NORCHP.2007.4481030}, year = 2007 }