%0 Conference Paper %1 conf/fccm/LiuQ17 %A Liu, Qiang %A Qian, HanJing %B FCCM %D 2017 %I IEEE Computer Society %K dblp %P 29 %T FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters. %U http://dblp.uni-trier.de/db/conf/fccm/fccm2017.html#LiuQ17 %@ 978-1-5386-4037-1

@inproceedings{conf/fccm/LiuQ17, added-at = {2023-03-24T00:00:00.000+0100}, author = {Liu, Qiang and Qian, HanJing}, biburl = {https://www.bibsonomy.org/bibtex/2aaa8ad67a82e2960a9d22e94ef8ca868/dblp}, booktitle = {FCCM}, crossref = {conf/fccm/2017}, ee = {https://doi.ieeecomputersociety.org/10.1109/FCCM.2017.16}, interhash = {66467b26873854013f7142528b4fba93}, intrahash = {aaa8ad67a82e2960a9d22e94ef8ca868}, isbn = {978-1-5386-4037-1}, keywords = {dblp}, pages = 29, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T12:36:34.000+0200}, title = {FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters.}, url = {http://dblp.uni-trier.de/db/conf/fccm/fccm2017.html#LiuQ17}, year = 2017 }