%0 Conference Paper %1 conf/date/HuangHL11 %A Huang, Keheng %A Hu, Yu %A Li, Xiaowei %B DATE %D 2011 %I IEEE %K dblp %P 58-63 %T Cross-layer optimized placement and routing for FPGA soft error mitigation. %U http://dblp.uni-trier.de/db/conf/date/date2011.html#HuangHL11 %@ 978-1-61284-208-0

@inproceedings{conf/date/HuangHL11, added-at = {2023-03-24T00:00:00.000+0100}, author = {Huang, Keheng and Hu, Yu and Li, Xiaowei}, biburl = {https://www.bibsonomy.org/bibtex/233d385150e0dca8ede1683f3ccc82a5a/dblp}, booktitle = {DATE}, crossref = {conf/date/2011}, ee = {https://doi.ieeecomputersociety.org/10.1109/DATE.2011.5763018}, interhash = {2ba40a8c67bb18db1080c8c282330ead}, intrahash = {33d385150e0dca8ede1683f3ccc82a5a}, isbn = {978-1-61284-208-0}, keywords = {dblp}, pages = {58-63}, publisher = {IEEE}, timestamp = {2024-04-10T06:49:01.000+0200}, title = {Cross-layer optimized placement and routing for FPGA soft error mitigation.}, url = {http://dblp.uni-trier.de/db/conf/date/date2011.html#HuangHL11}, year = 2011 }