%0 Conference Paper %1 9911325 %A Karrenbauer, Jens %A Klein, Simon %A Schönewald, Sven %A Gerlach, Lukas %A Blawat, Meinolf %A Benndorf, Jens %A Blume, Holger %B ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) %D 2022 %K 2022 l3s myown %P 265-268 %R 10.1109/ESSCIRC55480.2022.9911325 %T SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI %U https://ieeexplore.ieee.org/document/9911325/ %X To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm 2. The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.

@inproceedings{9911325, abstract = {To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm 2. The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.}, added-at = {2023-02-14T13:48:52.000+0100}, author = {Karrenbauer, Jens and Klein, Simon and Schönewald, Sven and Gerlach, Lukas and Blawat, Meinolf and Benndorf, Jens and Blume, Holger}, biburl = {https://www.bibsonomy.org/bibtex/2c06380d3895fe1fb25aec7470b37f6db/imsl3s}, booktitle = {ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)}, doi = {10.1109/ESSCIRC55480.2022.9911325}, interhash = {2df7a4cdb6420b15896f1e5483d8860a}, intrahash = {c06380d3895fe1fb25aec7470b37f6db}, keywords = {2022 l3s myown}, month = {Sep.}, pages = {265-268}, timestamp = {2023-02-14T13:48:52.000+0100}, title = {SmartHeaP - A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI}, url = {https://ieeexplore.ieee.org/document/9911325/}, year = 2022 }